OPC+OPC+ Cloud PlatformNYCU PAL / NSL Lab
Launch Platform啟動平臺
Next-generation computational lithography次世代計算微影

OPC+ Cloud Platform

Cloud-based freeform mask correction · GPU-accelerated OPC for semiconductor & photonics

雲端自由曲線光罩修正 · 以 GPU 加速的半導體與光子元件 OPC

Developed by PAL Lab & NSL Lab · National Yang Ming Chiao Tung University

由國立陽明交通大學 PAL 實驗室 與 NSL 實驗室 共同開發

Cloud native雲端原生GPU acceleratedGPU 加速50× faster快 50 倍Curvilinear support支援曲邊型光罩
Launch Platform啟動平臺 Watch demo觀看示範 Learn more了解更多
opc-cloud.com
OPC+ platform — Mask Rule Check with an inline layout viewer and region selection
The platform: mask rule check with the built-in layout viewer and analysis-region selection.平臺畫面：光罩規格檢測，內建版圖檢視器與分析區域框選。
50×faster than CPU OPC較 CPU OPC 更快
<2%load imbalance負載不平衡
12+GPUs in public cloud公有雲 GPU
GDS/OASISindustry-standard formats業界標準格式
Freeformcurvilinear mask support曲邊型光罩支援
Background背景

What is Optical Proximity Correction (OPC)?什麼是光學鄰近修正（OPC）？

Semiconductor and photonic devices are fabricated by projecting light through a patterned mask onto a photosensitive wafer—a process called photolithography [1]. Because the wavelength of the exposure source is comparable to, or larger than, the minimum feature sizes being printed, optical diffraction causes the projected image to deviate systematically from the intended design: line ends shorten, corners round off, and isolated features may fail to print entirely.

半導體與光子元件的製造，是將光線透過帶有圖案的光罩投影到感光晶圓上，這個過程稱為光學微影 [1]。由於曝光光源的波長與所要印製的最小特徵尺寸相當、甚至更大，光學繞射會使投影影像系統性地偏離設計：線端縮短、轉角圓化，孤立的特徵甚至可能完全無法成像。

Optical Proximity Correction (OPC) is the pre-distortion technique applied to the mask layout to compensate for these optical and process-induced effects, so that the final printed pattern on the wafer faithfully reproduces the designer's intent. Modern OPC is increasingly realized through Inverse Lithography Technology (ILT)—a full-mask optimization approach that directly solves for the mask shape required to produce a target wafer image [2].

光學鄰近修正（OPC）是預先對光罩版圖進行變形補償的技術，用以抵銷這些光學與製程效應，使晶圓上最終印出的圖案忠實呈現設計意圖。現代 OPC 越來越多以反向微影技術（ILT）實現——這是一種全光罩最佳化方法，直接求解能產生目標晶圓影像所需的光罩形狀 [2]。

OPC concept: target vs. OPC mask
Figure 1. The target layout (left, without correction) produces a blurred wafer image due to diffraction. The OPC-corrected mask (right) pre-distorts the design so the printed result faithfully reproduces the intended pattern.圖 1. 目標版圖（左，未修正）因繞射而產生模糊的晶圓影像；經 OPC 修正的光罩（右）預先變形設計，使印製結果忠實重現原始圖案。

Why is traditional OPC insufficient?傳統 OPC 為何不足？

Conventional OPC tools rely on CPU-based, rule-driven solvers designed for Manhattan geometries (rectilinear, axis-aligned shapes). They present three fundamental limitations as the industry advances toward photonics and curvilinear CMOS nodes:

傳統 OPC 工具依賴以 CPU 為基礎、規則導向的求解器，且是為曼哈頓幾何（直線、與軸對齊的形狀）所設計。隨著產業走向光子元件與曲邊型 CMOS 製程節點，它們暴露出三個根本限制：

Limitation限制Impact影響
Speed速度CPU-bound serial processing makes large-layout corrections extremely time-consuming—often requiring hours per job受限於 CPU 的序列處理，大型版圖的修正極為耗時，往往每個任務需要數小時
Cost & accessibility成本與可及性Commercial licenses are prohibitively expensive and operation requires specialized expertise, excluding startups and research institutions商用授權費用高昂，且操作需要專業知識，將新創公司與研究機構排除在外
Geometry constraints幾何限制Photonic integrated circuits and next-generation curvilinear CMOS nodes require freeform mask geometries that traditional tools cannot handle natively—forcing lossy polygonal approximation光子積體電路與次世代曲邊型 CMOS 節點需要自由曲線的光罩幾何，傳統工具無法原生處理，只能以有損的多邊形近似
Our solution我們的解決方案

Breaking the barriers of traditional OPC突破傳統 OPC 的障礙

OPC+ is a cloud-native, GPU-accelerated platform that democratizes advanced mask correction. By replacing CPU-bound solvers with massively parallel GPU computation and wrapping the entire workflow in an intuitive web interface, OPC+ removes the barriers of traditional tools while extending OPC capabilities to cutting-edge photonic and semiconductor applications [3].

OPC+ 是雲端原生、GPU 加速的平臺，讓先進的光罩修正不再是少數人的專利。它以大規模平行的 GPU 運算取代受限於 CPU 的求解器，並將整個工作流程包裝成直覺的網頁介面，在消除傳統工具門檻的同時，把 OPC 的能力延伸到最前沿的光子與半導體應用 [3]。

The platform is built around three core principles:

平臺圍繞三個核心原則打造：

Speed速度

CUDA multi-stream parallelism delivers 50× faster correction than CPU-based solvers. Jobs that previously required hours complete in minutes, enabling rapid design iteration [3][4].

CUDA 多串流平行化帶來較 CPU 求解器快 50 倍的修正速度。過去需要數小時的任務，如今數分鐘即可完成，讓設計迭代得以快速進行 [3][4]。

Accessibility可及性

A web-based GUI requires no scripting or deep OPC expertise. Upload a layout, configure scanner parameters, and submit. No hardware investment required—GPU clusters are provisioned on demand.

網頁圖形介面不需要撰寫腳本或深厚的 OPC 專業。上傳版圖、設定曝光機參數、送出即可。無需硬體投資——GPU 叢集依需求配置。

Generality通用性

Native curvilinear mask support enables OPC beyond digital CMOS, validated on photonic integrated circuits and large-area metasurfaces [5][4].

原生支援曲邊型光罩，使 OPC 能超越數位 CMOS，並已在光子積體電路與大面積超穎表面上得到驗證 [5][4]。

Validation驗證

SEM validation on fabricated devices實際製作元件的 SEM 驗證

The following Scanning Electron Microscope (SEM) images present fabricated device results demonstrating the direct, measurable impact of OPC correction on real photonic structures. All results were obtained from wafers processed at collaborating fabrication facilities.

以下掃描式電子顯微鏡（SEM）影像呈現實際製作的元件結果，展示 OPC 修正對真實光子結構直接且可量測的影響。所有結果皆來自合作製程單位所加工的晶圓。

Line pattern — line-end shortening線條圖案 — 線端縮短

Without OPC correction, diffraction at the tips of line features causes the printed ends to recede inward, resulting in lines that are shorter than the target design. This line-end shortening introduces critical dimension (CD) error along the line length axis. OPC pre-compensation extends the mask geometry at line ends so that the fabricated result matches the intended length.

未經 OPC 修正時，線條末端的繞射使印出的線端向內退縮，導致線條比目標設計更短。此線端縮短效應在線長方向引入關鍵尺寸（CD）誤差。OPC 預補償會延長光罩上的線端幾何，使製作結果符合預期長度。

Line pattern without OPC
Without OPC未經 OPC
Line pattern with OPC
With OPC經 OPC 修正

Figure 2. SEM images of fabricated line patterns. Scale bar: 5 µm.圖 2. 實際製作線條圖案的 SEM 影像。比例尺：5 µm。

Ring resonator — critical defect elimination環形共振器 — 消除致命缺陷

For photonic ring resonators, OPC correction is critical to device functionality. Without correction, the coupling gap region fails to open properly—a fatal fabrication defect that renders the device non-functional optically. With OPC, the waveguide geometry is accurately reproduced and the coupling region is fully resolved [5].

對光子環形共振器而言，OPC 修正攸關元件是否能運作。未經修正時，耦合間隙區域無法正確打開——這是致命的製程缺陷，會使元件在光學上完全失效。經 OPC 修正後，波導幾何被準確重現，耦合區域完整解析 [5]。

Ring resonator without OPC
Without OPC未經 OPC
Ring resonator with OPC
With OPC經 OPC 修正

Figure 3. SEM images of fabricated ring resonators. Scale bar: 5 µm (overview), 1 µm (inset).圖 3. 實際製作環形共振器的 SEM 影像。比例尺：5 µm（全圖）、1 µm（插圖）。

Metalens — sub-wavelength feature survival超穎透鏡 — 次波長特徵的保留

Metalenses rely on densely packed sub-wavelength nano-structures whose precise geometry determines the phase profile of the device. Without OPC, the photolithography process fails to resolve the smallest features—they are either significantly distorted or lost entirely—compromising the optical function of the device. With OPC, all features are faithfully reproduced after lithography, preserving the intended phase distribution across the aperture [5].

超穎透鏡依賴緊密排列的次波長奈米結構，其精確幾何決定元件的相位分佈。未經 OPC 時，光學微影無法解析最小的特徵——它們不是嚴重變形就是完全消失——損及元件的光學功能。經 OPC 修正後，所有特徵在微影後都被忠實重現，保留整個孔徑上預期的相位分佈 [5]。

Metalens without OPC
Without OPC未經 OPC
Metalens with OPC
With OPC經 OPC 修正

Figure 4. SEM images of fabricated metalens structures. OPC ensures survival of all sub-wavelength features critical to device phase control.圖 4. 實際製作超穎透鏡結構的 SEM 影像。OPC 確保所有攸關相位控制的次波長特徵得以保留。

Capabilities功能

Key features主要特色

GPU accelerationGPU 加速

Leveraging CUDA multi-stream image-level parallelism, OPC+ achieves 50× faster mask correction compared to CPU-based methods [3][4].

運用 CUDA 多串流的影像層級平行化，OPC+ 的光罩修正速度較 CPU 方法快 50 倍 [3][4]。

Cloud-native architecture雲端原生架構

Built on Kubernetes with elastic resource scheduling. OPC+ dynamically allocates GPU resources across public, private, or hybrid environments. No capital hardware expenditure required.

以 Kubernetes 建構並具備彈性資源排程。OPC+ 可在公有、私有或混合環境中動態配置 GPU 資源，無需硬體資本支出。

Native curvilinear mask support原生曲邊型光罩支援

OPC+ natively generates curvilinear masks without polygonal approximation, preserving optical phase and waveguide coupling efficiency in photonic applications [5].

OPC+ 原生產生曲邊型光罩、無需多邊形近似，在光子應用中保留光學相位與波導耦合效率 [5]。

Global inverse optimization全域反向最佳化

Full-mask ILT with contour-based L2 optimization achieves superior pattern fidelity and CD uniformity compared to rule-based windowed correction approaches [4][6].

以輪廓為基礎的 L2 全光罩 ILT 最佳化，相較規則式的視窗修正方法，達到更佳的圖案保真度與 CD 均勻度 [4][6]。

Predictable turnaround可預測的週轉時間

Two-tier dynamic workload scheduling maintains <2% execution imbalance across heterogeneous GPU nodes, enabling reliable and consistent job delivery [3].

兩層式動態工作負載排程在異質 GPU 節點間維持低於 2% 的執行不平衡，確保任務交付穩定一致 [3]。

Industry-standard formats業界標準格式

Seamless integration with existing EDA workflows through native support for GDS/OASIS layout files and CD-SEM calibration data.

原生支援 GDS/OASIS 版圖檔與 CD-SEM 校正資料，可無縫整合既有的 EDA 流程。

Workflow工作流程

Complete correction workflow完整的修正流程

OPC+ integrates three essential modules into a unified, automated pipeline — the same three steps you see in the platform's navigation. Each module can be configured independently or combined to match the requirements of a specific fabrication process.

OPC+ 將三個關鍵模組整合為統一、自動化的流程——也就是平臺導覽列中的三個步驟。每個模組可獨立設定，或依特定製程需求組合使用。

1

Physical model calibration微影模型建置

Analytical imaging models fitted to actual lithography process data using CD-SEM measurements. Accounts for scanner-specific, resist, and process variations [4].

以 CD-SEM 量測資料將解析成像模型擬合至實際微影製程，納入曝光機、光阻與製程的變異 [4]。

2

OPC correction光罩修正

Advanced full-mask inverse lithography with contour-based L2 optimization. Achieves holistic pattern fidelity superior to traditional EPE rule-based correction [4][6].

以輪廓為基礎的 L2 最佳化進行先進的全光罩反向微影，整體圖案保真度優於傳統以 EPE 規則為基礎的修正 [4][6]。

3

Aerial image simulation成像模擬

High-fidelity imaging simulation incorporating user-defined scanner parameters: exposure wavelength, numerical aperture (NA), spatial resolution, and illumination source configuration [1].

高保真度的成像模擬，納入使用者定義的曝光機參數：曝光波長、數值孔徑（NA）、空間解析度與照明光源設定 [1]。

In the platform: Litho Model Setting → Mask Correction → Imaging Simulation. The imaging step also includes contour simulation and mask rule check (MRC) with an inline layout viewer for choosing the analysis region.在平臺中對應：微影模型建置 → 光罩修正 → 成像模擬。成像步驟另包含 contour 模擬與光罩規格檢測（MRC），並內建版圖檢視器以框選分析區域。
Technical analysis技術分析

OPC+ vs. traditional OPC: a complete comparisonOPC+ 與傳統 OPC 的完整比較

A systematic comparison of OPC+ Cloud against conventional on-premises OPC tools across architecture, performance, and business dimensions.

從架構、效能與商業面向，系統性比較 OPC+ 雲端服務與傳統本地 OPC 工具。

Category類別Traditional OPC傳統 OPCOPC+ CloudOPC+ 雲端Business benefit商業效益
Mask geometry support光罩幾何支援Manhattan-based (rectilinear only)以曼哈頓幾何為主（僅直線）Native curvilinear and freeform原生曲邊型與自由曲線Preserves optical phase and device performance保留光學相位與元件效能
Design conversion設計轉換Requires polygon fracturing / Manhattanization需要多邊形切割／曼哈頓化No geometry approximation required無需幾何近似Eliminates layout-induced performance loss消除版圖近似造成的效能損失
Optimization method最佳化方法Local rule-based or windowed EPE局部規則式或視窗 EPEGlobal full-mask inverse optimization全域全光罩反向最佳化Higher pattern fidelity and CD uniformity更高的圖案保真度與 CD 均勻度
GPU utilizationGPU 使用Limited or static GPU assignment有限或靜態的 GPU 指派Cost-performance-aware dynamic allocation考量成本效能的動態配置Optimal cost vs. throughput tradeoff最佳的成本與產能取捨
Parallelism平行化Limited job-level parallelism有限的任務層級平行CUDA multi-stream image-level parallelismCUDA 多串流影像層級平行Faster processing of large layouts更快處理大型版圖
Workload scheduling工作負載排程Static or FIFO靜態或先進先出Two-tier dynamic scheduling兩層式動態排程Balanced execution across heterogeneous GPUs異質 GPU 間執行平衡
Turnaround predictability週轉時間可預測性Variable, bottleneck-prone變動大、易出現瓶頸<2% execution imbalance across nodes節點間執行不平衡低於 2%Reliable delivery schedules可靠的交付時程
Deployment model部署模式On-premises only僅限本地部署Public, private, or hybrid cloud公有、私有或混合雲Fits foundry security and IT policies符合晶圓廠的資安與 IT 政策
Manufacturing validation製造驗證Logic-centric benchmarks以邏輯電路為主的基準Validated on photonics and metasurfaces已在光子元件與超穎表面驗證Proven beyond digital CMOS超越數位 CMOS 的實證
Future readiness未來準備度Limited for curvilinear CMOS對曲邊型 CMOS 支援有限Ready for next-generation curvilinear nodes為次世代曲邊型節點做好準備Enables new process node offerings可提供新製程節點服務
Capacity planning硬體容量規劃

How much hardware do you need?您需要多少硬體？

Estimate the GPU fleet to finish OPC on your layout by your deadline — grounded in measured runs on fully-patterned tiles (1.6 s per correction tile on an RTX 4090; an RTX Pro 6000 runs four isolated MIG workers for ≈0.84 s per tile per card — about 1.9× a 4090). Upload a GDS or OASIS file to auto-detect the die size and pattern density, or set them directly. Everything runs in your browser — your file never leaves your computer.

估算在期限內完成您版圖 OPC 所需的 GPU 數量——依據實測結果（滿圖案圖塊：RTX 4090 每個修正圖塊 1.6 秒；RTX Pro 6000 以四個獨立 MIG 工作單元運行，每張卡約 0.84 秒/圖塊，約為 4090 的 1.9 倍）。上傳 GDS 或 OASIS 檔案可自動偵測晶片尺寸與圖案密度，或直接手動設定。所有計算都在您的瀏覽器中進行——檔案不會離開您的電腦。

Your layout您的版圖
Click or drag & drop — die size and pattern density are detected automatically.
Your file is analyzed locally and never leaves your browser.點選或拖曳檔案——自動偵測晶片尺寸與圖案密度。
檔案僅在本機分析，不會離開瀏覽器。
Width寬度 16 mm
Height高度 16 mm
Pixel size像素大小 2.6 nm
Production OPC runs 2–5 nm. Finer pixel → far more tiles.量產 OPC 通常為 2–5 nm；像素越細，圖塊數量越多。
Pattern density圖案密度 10%
Deadline期限 3 days天
Recommended · RTX Pro 6000建議配置 · RTX Pro 6000
—
Correction workload修正工作量
—
Estimated completion預估完成時間
—
Prep & assembly前處理與組裝
—
Estimated hardware investment預估硬體投資
GPUUnits數量Finish完成時間Total $總金額
Unmarked rows are measured on fully-patterned tiles — sparse, mostly-empty regions run far faster, so these are conservative planning values (4090: 1.63 s per tile, ≈2,200 tiles/hr). The measurement is our September 2026 fleet verification — 229 fully-patterned tiles per node under one pinned recipe — carried to the platform’s production settings by the factor measured on the same nodes in August. Rows marked † are projected from memory bandwidth, which our measurements show governs throughput. The Pro 6000 figure runs each card as four isolated MIG workers (3.37 s per tile per worker → ≈0.84 s per tile per card, about 1.9× the throughput of a 4090). A recommended Pro 6000 node ships fully configured — 96 GB per card, ECC memory, the OPC+ software stack, and support. Treat this as a planning estimate; we confirm the exact figure from a calibration run on your own layout. Hardware prices are indicative market values for September 2026; the GDDR7 memory shortage has moved them sharply, and the RTX 4090 and RTX 4070 SUPER are discontinued, so those are used-market prices.未標記的列為滿圖案圖塊上的實測值——稀疏、大多空白的區域會快得多，因此這些是保守的規劃值（4090：每圖塊 1.63 秒，約 2,200 圖塊/小時）。量測來自 2026 年 9 月的機群驗證（每個節點 229 個滿圖案圖塊、同一組固定配方），再依 8 月在相同節點上量得的係數換算到平臺的量產設定。標記 † 的列依記憶體頻寬推估，我們的量測顯示頻寬決定產能。Pro 6000 的數值是每張卡以四個獨立 MIG 工作單元運行（每單元 3.37 秒/圖塊 → 每卡約 0.84 秒/圖塊，約為 4090 的 1.9 倍）。建議的 Pro 6000 節點出貨即完整配置——每卡 96 GB、ECC 記憶體、OPC+ 軟體堆疊與支援。此為規劃估算；確切數字將以您版圖的校正試跑確認。硬體價格為 2026 年 9 月的市場參考值；GDDR7 記憶體短缺已使價格大幅變動，RTX 4090 與 RTX 4070 SUPER 已停產，其價格為二手市場行情。

How do I estimate pattern density?如何估算圖案密度？

Density is the share of tiles that contain any pattern — not the area your polygons cover. Each tile is 2048 px across, and a tile counts as soon as it holds a single feature. Scattered small structures therefore push density higher than raw area suggests. Uploading your GDS/OASIS file above measures this automatically on the same tile grid the estimator uses. If you can't upload and are unsure, pick the higher band — it's the safer way to size hardware.

密度指的是含有任何圖案的圖塊比例——不是多邊形所覆蓋的面積。每個圖塊寬 2048 px，只要含有單一特徵就會被計入。因此分散的小結構會讓密度高於面積所暗示的值。在上方上傳 GDS/OASIS 檔案即可自動量測，使用與估算器相同的圖塊網格。若無法上傳且不確定，請選擇較高的區間——這是較安全的硬體規劃方式。

If your layout looks like…若您的版圖像是…Use請採用
Isolated test structures or sparse gratings on a mostly empty field大片空白區域上的孤立測試結構或稀疏光柵1–3%
Labels, alignment marks, a few device blocks on a large die大晶片上的標籤、對準記號與少數元件區塊5–10%
Mixed test chip, periodic arrays, photonic device banks混合測試晶片、週期陣列、光子元件陣列10–20%
Dense periodic arrays, metasurface / metalens, full-field patterning密集週期陣列、超穎表面／超穎透鏡、全區圖案化60–80%
Rule of thumb: if your pattern is spread across most of the die, you're in the upper bands; if it's concentrated in a small area of a big die, you're in the lower ones. These bands come from measured production layouts — a calibration run on your own file returns the exact figure.經驗法則：若圖案分布在晶片大部分區域，屬於較高區間；若集中在大晶片的小區域，則屬於較低區間。這些區間來自實測的量產版圖——以您的檔案進行校正試跑可得到精確數值。
Getting started開始使用

How to use the OPC+ Cloud Platform如何使用 OPC+ 雲端平臺

Prerequisites事前準備

  • Target layout file in GDS or OASIS format
  • GDS 或 OASIS 格式的目標版圖檔
  • Scanner parameters (exposure wavelength, numerical aperture, illumination configuration)
  • 曝光機參數（曝光波長、數值孔徑、照明設定）
  • (Optional) CD-SEM calibration data for physical model fitting
  • （選用）用於物理模型擬合的 CD-SEM 校正資料

Step by step操作步驟

  1. Access the platform. Go to opc-cloud.com and register an account. The interface is available in English and Traditional Chinese.
  2. 進入平臺。前往 opc-cloud.com 註冊帳號。介面提供英文與繁體中文。
  3. Upload your design. Upload your target layout (GDS/OASIS) — it appears in the built-in viewer — and enter the scanner parameters for your process.
  4. 上傳設計。上傳目標版圖（GDS/OASIS）——會直接顯示在內建檢視器中——並輸入製程的曝光機參數。
  5. Configure calibration (optional). Upload CD-SEM measurement data if physical model calibration is required for your fabrication environment.
  6. 設定校正（選用）。若您的製程環境需要物理模型校正，請上傳 CD-SEM 量測資料。
  7. Submit and monitor. Submit the job to the GPU cluster and track its progress in the job list.
  8. 送出並追蹤。將任務送至 GPU 叢集，並在工作清單中追蹤進度。
  9. Download results. Retrieve the corrected mask layout (GDS/OASIS), ready for mask writing and manufacturing.
  10. 下載結果。取得修正後的光罩版圖（GDS/OASIS），可直接用於光罩寫入與製造。
opc-cloud.com
OPC+ dashboard
Figure 5. The OPC+ dashboard: workflow steps, recent jobs and usage at a glance.圖 5. OPC+ 儀表板：工作流程步驟、最近的任務與使用統計一目瞭然。
Applications應用

Target applications目標應用

Semiconductor manufacturing半導體製造

  • Advanced process node development (7 nm, 5 nm, 3 nm and beyond)
  • 先進製程節點開發（7 nm、5 nm、3 nm 及以下）
  • Semiconductor foundries and mask shops
  • 晶圓代工廠與光罩廠
  • Fabless design houses
  • 無晶圓廠設計公司
  • Research and development laboratories
  • 研發實驗室

Photonic integrated circuits光子積體電路

  • Silicon photonic waveguides and ring resonators
  • 矽光子波導與環形共振器
  • Apodized grating couplers
  • 變跡光柵耦合器
  • Metasurfaces and metalenses
  • 超穎表面與超穎透鏡
  • Curvilinear photonic patterns
  • 曲邊型光子圖案

Research & prototyping研究與原型

  • Rapid design iteration and process exploration
  • 快速設計迭代與製程探索
  • Academic research in computational lithography
  • 計算微影的學術研究
  • High-volume manufacturing tape-out support
  • 量產下線支援
Deployment部署

Flexible deployment models彈性的部署模式

OPC+ offers three deployment configurations to accommodate varying security, performance, and budgetary requirements.

OPC+ 提供三種部署方式，以因應不同的資安、效能與預算需求。

Public cloud公有雲

Managed cluster of 12+ GPUs with optimal job scheduling and resource utilization.

由 12 張以上 GPU 組成的代管叢集，具備最佳的任務排程與資源使用率。

No infrastructure management or maintenance overhead.

無需管理或維護基礎設施。

Private cloud私有雲

Custom on-premises deployment with maximum IP security and data isolation.

客製化的本地部署，提供最高等級的智財安全與資料隔離。

Dedicated resources with full administrative control.

專屬資源，完整的管理控制權。

Hybrid model混合模式

Combines public and private infrastructure with configurable resource allocation per workload sensitivity.

結合公有與私有基礎設施，依工作負載敏感度配置資源。

Balances cost, performance, and data security requirements.

兼顧成本、效能與資料安全需求。

Credibility可信度

Industry validation & partnerships產業驗證與合作夥伴

OPC+ is jointly developed by the Photonics and Advanced Lithography Laboratory (PAL Lab) and the Network and System Laboratory (NSL Lab) at National Yang Ming Chiao Tung University (NYCU). The platform has been validated through collaborative engagements with leading semiconductor and photonics research institutions, bridging cutting-edge academic research in computational lithography with real-world industrial fabrication requirements [3][5].

OPC+ 由國立陽明交通大學（NYCU）的光子與先進微影實驗室（PAL Lab）與網路與系統實驗室（NSL Lab）共同開發。平臺已透過與領先的半導體及光子研究機構合作獲得驗證，將計算微影的尖端學術研究與真實的產業製造需求連結起來 [3][5]。

Taiwan Semiconductor Research Institute (TSRI)University of Southampton, UK

Supported by the National Science and Technology Council (NSTC), Taiwan.

由臺灣國家科學及技術委員會（NSTC）支持。

Platform access平臺存取

Watch the demo觀看示範

What OPC is and why chips need it: lithography, the blur, and how OPC+ reshapes the mask. Subtitles: English / 中文.認識 OPC：微影、光學模糊，以及 OPC+ 如何重塑光罩。字幕：English / 中文。 Open on YouTube在 YouTube 開啟

The platform is currently available for research and professional use. Register directly at the platform portal, or contact the team below to discuss access for industrial applications.

平臺目前開放研究與專業用途。您可直接在平臺入口註冊，或聯繫下方團隊洽談產業應用的使用方式。

Launch Platform啟動平臺 Watch on YouTube在 YouTube 觀看
https://opc-cloud.com
Literature文獻

References參考文獻

The following publications document the research and validation underpinning the OPC+ platform.

以下著作記錄了支撐 OPC+ 平臺的研究與驗證。

Foundational references基礎文獻
  • [1] C. Mack, Fundamental Principles of Optical Lithography: The Science of Microfabrication. John Wiley & Sons, 2007.
  • [2] L. Pang, "Inverse lithography technology: 30 years from concept to practical, full-chip reality," Journal of Micro/Nanopatterning, Materials, and Metrology, vol. 20, no. 3, pp. 030901–030901, 2021.
Research publications研究著作
  • [3] S.-Y. Wang et al., "Providing optimal optical proximity correction cloud services for the semiconductor industry," in IEEE International Conference on Cloud Computing Technology and Science (CloudCom), IEEE, 2025.
  • [4] P.-H. Fang and P. Yu, "Tackling data inconsistency and runtime issues in inverse lithography technology (ILT) with comparative convergence study," in DTCO and Computational Patterning III, vol. 12954, SPIE, 2024, p. 129541E.
  • [5] H.-L. Liu et al., "Intelligent proximity correction enabled large-area metasurfaces by KrF photolithography," IEEE Access, vol. 13, pp. 195517–195525, 2025.
  • [6] Y. Shen, N. Wong, and E. Y. Lam, "Level-set-based inverse lithography for photomask synthesis," Optics Express, vol. 17, no. 26, pp. 23690–23701, 2009.
  • [7] K.-H. Wang, P.-H. Fang, and P. Yu, "Practical inverse mask synthesis via data-efficient physics-informed neural networks (PINN) model," in DTCO and Computational Patterning IV, vol. 13425, SPIE, 2025.
  • [8] P.-H. Fang, Y.-S. Chen, J.-S. Wu, and P. Yu, "Inverse reticle optimization with quantum annealing and hybrid solvers," IEEE Access, vol. 12, pp. 33069–33078, 2024.
Contact聯絡

Get in touch與我們聯繫

Interested in accessing the OPC+ Cloud Platform or exploring research collaboration? Contact the team below.

想使用 OPC+ 雲端平臺，或探討研究合作？請聯繫下方團隊。

Principal investigator計畫主持人Prof. Peichen Yu余沛慈 教授
Emailpeichen.yu@nycu.edu.tw
Phone電話+886-3-5712121 ext. 56357
Platform平臺https://opc-cloud.com/
PAL LabPhotonics & Advanced Lithography光子與先進微影
NSL LabNetwork and System Laboratory網路與系統實驗室
Institution機構National Yang Ming Chiao Tung University國立陽明交通大學
Address地址No. 1001 University Road, East District, Hsinchu City 300, Taiwan300 新竹市東區大學路 1001 號